The present invention relates to high speed VLSI circuit testing. Apparatus is provided for reducing the memory requirements of an integrated circuit tester. Specifically, a programmable buffer memory is disclosed which provides an architecture which can change a minor number of bits of a test data field while maintaining the remaining data bits the same.
Multiple pin electronic circuit devices have grown in complexity to include in one VLSI structure 20,000 different logic blocks. The present course of developments suggests that VLSI structures will in the future include 100,000 logic blocks. Testing of VLSI structures requires that the circuits be activated, and a plurality of tests performed at a rate which will permit high volume testing. As a minimum, current VLSI structures require approximately 100,000 cycles of test data to be applied. For instance, a VLSI structure of 20,000 logic blocks may include 16 pins of external connections. To test such a device, one byte of information for each pin may be necessary, and 100,000 separate bytes necessary to completely test the structure. As such, to arrange test data in a memory for successive application to the VLSI structure requires storage of approximately 1.6.times.10.sup.6 bytes of information. Both the loading of these quantities of data and reading out the loaded test data will require in a conventional memory a run time which reduces the overall throughput of the testing system.
The prospect of larger VLSI structures increases the number of test cycles exponentially. As such, the data requirements for such VSLI structures increases the memory storage requirements exponentially, incurring still further delays in reading in and out test data for testing a given device.
Attempts to reduce the total amount of data required in a high speed testing device are disclosed in U.S. Pat. Nos. 3,873,818 and 4,291,404. The system of U.S. Pat. No. 3,873,818 provides for efficient storage of serial test patterns in a tester memory which is configured for parallel patterns. The patented system is efficient for shift register strings with a length equal or nearly equal to the number of bits per word in the tester memory. As the difference between the number of bits per word and length of a tested shift register string changes, the data compaction provided by the patented technique is less.
U.S. Pat. No. 4,291,404 provides a program method for storing character sets which represents only changes from a previous set. The system of the U.S. Pat. No. 4,291,404 does not compact the test data itself but rather provides for an improved method for uniquely identifying characters which are to change.
The present invention provides for yet another technique for compacting test data such that overall memory storage requirements are reduced, avoiding the lengthy delays of loading and unloading expensive memories.